1. Field of the Invention
The present invention relates to non-volatile semiconductor memory cells and more particularly to a method and apparatus for erasing data stored in electrically erasable programmnable read only memories (EEPROMs) that reduces band-to-band leakage current.
2. Description of the Related Art
Conventional erasable programmable read only memories (EPROMs) include a multiplicity of memory cells. Each memory cell of a typical metal oxide semiconductor device has a floating gate layer located underneath a control gate layer. A channel layer is defined by drain and source regions on the surface of a semiconductor substrate. The floating gate layer lies over the channel layer and is completely insulated from other portions by an insulating layer such as a SiO.sub.2 layer.
Programming of data in the EPROM is usually carried out by applying 10 to 20 or more volts between the drain and source regions and applying an appropriate voltage to the control gate. Application of these voltages cause electrons to be accelerated across the channel layer, thereby producing electron-hole pairs by impact ionization. Once these electrons gain sufficient energy, they overcome the potential barrier of a gate oxide layer on the channel and inject into the floating gate layer. The injected electrons increase a threshold voltage of the memory cell. Thus, the memory cell can store a logic state "1" or "0" different from the initial erased state.
In an erasing operation, ultra-violet (UV) light is irradiated to the floating gate. Electrons stored in the floating gate absorb the exiting UV energy. The exiting electrons are carried away to the substrate through the gate oxide, causing the cells to store the erased state.
One improvement for such EPROMs is an electrically erasable and programmable read only memory (EEPROM). The EEPROM includes a control circuit for controlling programming and erasing operations. A voltage multiplying circuit generates high voltages, necessary for programming and erasing data from a single power source, such as 5 volts. EEPROMs are currently in wider use than EPROMs due to the simplicity of their programming and erasing. For example, one use for EEPROMS is in integrated circuit cards.
Referring to FIG. 1, symmetrical source region 6 and drain region 4 are doped with N+ impurities and are formed on a p-type semiconductor substrate 2. The source region 6 and drain region 4 are separated by a channel region over which is positioned a tunnel oxide layer having a thickness of about 100 .ANG.. A floating gate 8 is positioned on the tunnel oxide layer. An intermediate insulating layer of oxide-nitride-oxide (ONO) having a thickness of about 250 .ANG. is formed on the floating gate 8. A control gate 10 is positioned on the intermediate insulating layer. Thus, the transistor cell has a stack type structure.
Another prior art EEROM structure is shown in FIG. 2 and an EEPROM structure used in the present invention is shown in FIG. 3. The EEPROM structures in FIGS. 2 and 3 are substantially identical to the structure shown in FIG. 1, except for the technique and structure for erasing data. Thus, the explanation of the structures shown in FIGS. 2 and 3 will be omitted to avoid duplication.
Referring to FIG. 1, the cell is erased by applying a high voltage Vpp, such as 12 volts, to the source region 6, holding the control gate 10 and the substrate 2 at ground potential and floating the drain region 4. This erasing approach has an advantage of reducing the applied erase voltage Vpp to about 12 volts as compared with a bulk erasing in which an erase voltage of about 20 volts is applied to the substrate.
The potential difference of 12 volts between the substrate 2 and the source region 6 produces a leakage current. Also, the potential difference of 12 volts between the source region 6 and the control gate 10 through the thin tunnel oxide causes a portion of the source region 6, overlapping the floating gate 8, to be deep-depleted. A small amount of charge is injected into the thin tunnel oxide layer, lowering the potential barrier of the tunnel oxide, for electron tunneling (i.e. causing band-bending). Thus, the presence of the high potential difference between the source region 6 and control gate 10 results in another leakage current referred to as a band-to-band leakage current.
These leakage currents disturb normal erasing operations of the cell. For example, a typical EEPROM chip with a single power supply includes a voltage multiplying circuit for generating high erase and program voltages. If a block erasing operation of the chip is performed, a multiplicity of cells in the block must be simultaneously erased. Due to the leakage currents in each cell, the constant current capacity of the voltage multiplying circuit is insufficient for erasing all of the cells in the block. Thus, the cells cannot be erased.
FIG. 2 shows a prior art method of erasing data in a transistor cell. Erasing is performed by applying a supply voltage Vcc to a N+ source region 6, applying negative 10 volts to control gate 10, floating N+ drain region 4 and grounding the substrate 2. The lowered voltage of the source region decreases a source-substrate junction leakage current. However, the potential difference between the source region 6 and the control gate 10 does not considerably reduce the band-to-band leakage current. The electric field across the thin tunnel oxide layer is slightly greater than that in FIG. 1 and the electron-tunneling induced hole generation in the oxide layer is no less than that in FIG. 1. Thus, the transistor in FIG. 2 is no more effective in reducing the total leakage current than the transistor in FIG. 1.
As discussed above, electron tunneling, alternatively referred to as Fowler-Nordheim tunneling, occurs through a small tunneling region of the thin tunnel oxide layer overlapping the source region 6 and the floating gate 10. Since reprogramming cells requires the cells also be erased, every cell must generally keep a constant threshold voltage over a certain number of program-erase cycles. In the case of block erasing, threshold voltages of cells (bits) in the block must be densely distributed at a desired voltage, regardless of the number of program-erase cycles.
The tunnel oxide layer at the small tunneling region is stressed by the repeated erasing cycles. Repeated erasing cycles increase the number of holes trapped in the oxide layer causing changes in the threshold voltage. Variations in manufacturing conditions also cause variations in oxide thickness. This means that every cell in the block may not be erased to the same desired threshold voltage. Thus, block erased cells might not have a close distribution of threshold voltages. Therefore, it is necessary that during the erasing operation of the chip, the holes trapped in the tunnel oxide layer are reduced.
It is therefore an object of the present invention to provide a method of reducing band-to-band leakage current during erasing operations in nonvolatile semiconductor memory cells.
It is another object of the present invention to reduce holes trapped in a thin tunnel oxide during erasing operations in a nonvolatile semiconductor memory cell.